AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 327
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
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18.6.6.2
Figure 18-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins
18.6.6.3
32117C–AVR-08/11
A[AD_MSB:2]
CLK_SMC
D[15:0]
NCS0
NWE
NRD
TDF optimization enabled (MODE.TDFMODE = 1)
TDF optimization disabled (MODE.TDFMODE = 0)
Read access on NCS0 (NRD controlled)
When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.
Figure 18-21 on page 327
controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRDHOLD = 4; READMODE = 1 (NRD controlled)
NWESETUP = 3; WRITEMODE = 1 (NWE controlled)
TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).
When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.
Figure 18-22 on page
the cases:
• read access followed by a read access on another chip select.
• read access followed by a write access on another chip select.
NRDHOLD = 4
328,
TDFCYCLES = 6
shows a read access controlled by NRD, followed by a write access
Figure 18-23 on page 328
Read to Write
Wait State
NWESETUP = 3
Write access on NCS0 (NWE controlled)
and
Figure 18-24 on page 329
AT32UC3C
illustrate
327
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