AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 352

• Manufacturer Part Number: AT32UC3C264C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C264C

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 19-3. SDRAM Device Initialization Sequence
19.7.2
32117C–AVR-08/11
SDRAMC_A[12:11]
SDRAMC_A[9:0]
SDCKE
SDWE
SDCK
SDCS
RAS
CAS
DQM
SDRAM Controller Write Cycle
A10
Inputs Stable for
200 usec
After initialization, the SDRAM devices are fully functional.
The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of
the active row in each bank, thus maximizing performance. To initiate a burst access, the
SDRAMC uses the transfer type signal provided by the master requesting the access. If the next
access is a sequential write access, writing to the SDRAM device is carried out. If the next
access is a write-sequential access, but the current access is to a boundary page, or if the next
access is in another row, then the SDRAMC generates a precharge command, activates the
new row and initiates a write command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge and active (t
and write (t
19.8.3. This is described in
Precharge All Banks
quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or
781 (7.81 µs x 100 MHz).
RCD
) commands. For definition of these timing parameters, refer to the
t
RP
1st Auto Refresh
Figure 19-4 on page
8th Auto Refresh
353.
t
RC
RP
) commands and between active
LMR Command
AT32UC3C
t
MRD
Valid Command
Section
352