AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 56

• Manufacturer Part Number: AT32UC3C264C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C264C

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32117C–AVR-08/11
Figure 7-3.
In addition to the listed reset types, the JTAG & AWIRE can keep parts of the device statically
reset. See JTAG and AWIRE documentation for details.
Table 7-4.
When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip. Refer to the module
configuration chapter to know the effect of the different reset events.
The table located in the module configuration chapter lists parts of the device that are reset,
depending on the reset source.The cause of the last reset can be read from the RCAUSE regis-
ter. This register contains one bit for each reset source, and can be read during the boot
sequence of an application to determine the proper action to be taken.
Reset source
Power-on Reset
External Reset
Brownout Reset
CPU Error
Watchdog Timer
OCD
R E S ET _N
P ow er-O n
B row nout
D etector
D etector
W atchdog R eset
Reset Controller Block Diagram
Reset Description
AW IR E
JTAG
O C D
Description
Supply voltage below the power-on reset detector threshold
voltage
RESET_N pin asserted
Supply voltage on VDDCORE below the brownout reset
detector threshold voltage
Caused by an illegal CPU access to external memory while
in Supervisor mode
See Watchdog Timer documentation.
See On-Chip Debug documentation
R C _R C A U SE
C ontroller
R eset
O C D , AST, W D T,
C P U , H S B , P B x
C lock G enerator
AT32UC3C
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