AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 189

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.3
Figure 13-1. PLL with Control Logic and Filters
13.5.3.1
32145A–12/2011
Source
clocks
PLLOSC
PLL Operation
Enabling the PLL
f
REF
Divider
PLLDIV
Input
used in Shutdown mode, PINSEL must be written to one, and XIN32_2 and XOUT32_2 must be
used.
Rev: 1.1.0.0
The device contains one Phase Locked Loop (PLL), which is controlled by the Phase Locked
Loop Interface (PLLIF). The PLL is disabled by default, but can be enabled to provide high fre-
quency source clocks for synchronous or generic clocks. The PLL can use different clock
sources as reference clock, please refer to the “PLL Clock Sources” table in the SCIF Module
Configuration section for details. The PLL output is divided by a multiplication factor, and the
PLL compares the phase of the resulting clock to the reference clock. The PLL will adjust its out-
put frequency until the two compared clocks phases are equal, thus locking the output frequency
to a multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent the connected digital logic
from receiving a too high frequency and thus become unstable.
The PLL can be configured by writing the PLL Control Register (PLLn). To prevent unexpected
writes due to software bugs, write access to the PLLn register is protected by a locking mecha-
nism, for details please refer to the UNLOCK register description.
Before the PLL is enabled it must be set up correctly. The
selects a source for the reference clock. The PLL Multiply Factor (PLLMUL) and PLL Division
Divider
Output
PLLMUL
Detector
Phase
PLLOPT[0]
VCO
f
vco
1/2
Counter
Lock
PLLOPT[1]
0
1
AT32UC3L0128/256
PLL Oscillator Select field (
f
PLL
Mask
Lock bit
PLL clock
PLLOSC)
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