AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 580
AT32UC3L0256
Manufacturer Part Number
AT32UC3L0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L0256-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL
Quantity:
270
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3L0128 PDF datasheet #3
- AT32UC3L0128 PDF datasheet #4
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- Download datasheet (13Mb)
• ETRGEDG: External Trigger Edge Selection
• LDBDIS: Counter Clock Disable with RB Loading
• LDBSTOP: Counter Clock Stopped with RB Loading
• BURST: Burst Signal Selection
• CLKI: Clock Invert
• TCCLKS: Clock Selection
32145A–12/2011
ETRGEDG
TCCLKS
BURST
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
0: TIOB is used as an external trigger.
1: Counter clock is disabled when RB loading occurs.
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
0: Counter clock is not stopped when RB loading occurs.
1: The counter is incremented on falling edge of the clock.
0: The counter is incremented on rising edge of the clock.
Burst Signal Selection
The clock is not gated by an external signal
XC0 is ANDed with the selected clock
XC1 is ANDed with the selected clock
XC2 is ANDed with the selected clock
Clock Selected
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Edge
none
rising edge
falling edge
each edge
AT32UC3L0128/256
580
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