AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 555

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.7.14
Name:
Access Type:
Offset:
Reset Value:
•
32145A–12/2011
CHER: Channel Event Response
31
23
15
7
0: The increase event will increase the duty cycle value by one in a PWM period for the corresponding channel and the
decrease event will decrease the duty cycle value by one.
1: The increase event will decrease the duty cycle value by one in a PWM period for the corresponding channel and the
decrease event will increase the duty cycle value by one.
The events are taken into account when the common timebase counter reaches its top.
If more than one CHERR register is present, CHERR0 controls channels 31-0 and CHERR1 controls channels 64-32 and so on.
Channel Event Response Register
30
22
14
6
CHERRm
Read/Write
0x34+m*0x10
0x00000000
29
21
13
5
28
20
12
4
CHER
CHER
CHER
CHER
27
19
11
3
26
18
10
2
AT32UC3L0128/256
25
17
9
1
24
16
8
0
555