AT89LP3240 Atmel Corporation, AT89LP3240 Datasheet - Page 108

• Manufacturer Part Number: AT89LP3240
• Manufacturer: Atmel Corporation

Specifications of AT89LP3240

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

18.1.5
Figure 18-6. Typical Data Transmission
18.2
108
SDA
SCL
Multi-master Bus Systems, Arbitration and Synchronization
AT89LP3240/6440
Combining Address and Data Packets Into a Transmission
START
Addr MSB
1
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 18-6
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the master with the shortest high period. The low period of the combined clock is equal to
the low period of the master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low Time-out periods when the combined
SCL line goes high or low, respectively.
• An algorithm must be implemented allowing only one of the masters to complete the
• Different masters may use different SCL frequencies. A scheme must be devised to
2
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slaves
(i.e., the data being transferred on the bus must not be corrupted).
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
SLA+R/W
Addr LSB
shows a typical data transmission. Note that several data bytes can be transmitted
7
R/W
8
ACK
9
Data MSB
1
2
Data Byte
7
Data LSB
8
ACK
9
3706C–MICRO–2/11
STOP