AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 169
AT89LP51ED2
Manufacturer Part Number
AT89LP51ED2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51ED2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
2.25
Eeprom (bytes)
4096
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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21.2
21.3
3714A–MICRO–7/11
Temperature Sensor
DAC Operation
A timing diagram of an ADC conversion is shown in
ADC clock cycles to complete. The analog input is sampled during the third cycle of the conver-
sion and is held constant for the remainder of the conversion. At the end of the conversion, the
interrupt flag, ADIF, is set and the result is written to the data registers. An additional 1 ADC
clock cycle and up to 2 system clock cycles may be required to synchronize ADIF with the rest of
the system. The results in DADH/DADL remain valid until the next conversion completes. DADH
and DADL are read-only registers during ADC mode.
Figure 21-3. ADC Timing Diagram
ADC input channel 6 is not connected to a port pin. Instead it has a connection to two internal
special functions: a temperature sensor and a voltage supply monitor. When ACS = 6 the IREF
bit in DADI selects between them, such that IREF = 0 selects the voltage supply channel and
IREF = 1 select the temperature sensor channel. Both these modes use the internal 1.0V refer-
ence for the full scale and the negative input. The temperature sensor outputs a voltage that is
proportional to the ambient operating temperature. The uncalibrated output is linear and is suit-
able for relative temperature measurements. The supply voltage channel is the device supply
level divided-by-8. It can be used to find the actual operating voltage of the device.
The following conversion formulae apply for temperature sensor and supply monitor modes:
The DAC converts a 10-bit signed digital value to an analog output voltage through successive
approximation. The DAC always operates in differential mode, outputting a voltage differential
between its positive (P2.2) and negative (P2.3) outputs with a common mode of V
imum value represents zero difference and the maximum values represent a difference of
positive or negative V
The DAC is enabled by setting the ADCE and DAC bits in DADC. Some settling time is required
for the reference circuits to stabilize after the DAC is enabled. The DAC does not have multiple
Cycle Number
ADC Clock
GO/BSY
ADIF
DADH
DADL
1
(Supply Voltage)
REF
2
(Temp Sensor)
Initialize Circuitry
minus 1 LSB.
3
AT89LP51RD2/ED2/ID2 Preliminary
4
5
Sample & Hold
One Conversion
6
ADC
ADC
7
=
8
=
511
511
Figure
9
×
×
(
----------------------------------------------- -
10
VDD
V
------------------------------------ -
Conversion
Complete
TEMP
21-3. The conversion requires 13
11
V
⁄
V
REF
REF
–
8
12
) V
V
–
REF
13
REF
MSB of Result
LSB of Result
Next Conversion
1
DD
/2. The min-
2
Initialize
3
169
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