AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 201
AT89LP51ED2
Manufacturer Part Number
AT89LP51ED2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51ED2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
2.25
Eeprom (bytes)
4096
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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Figure 24-6. Diagram Context Description
3714A–MICRO–7/11
Access Via
Specific
Protocol
Access From
User
Application
Table 24-11
Table 24-11. Bootload Definitions
On
Mnemonic
BSB
HW/HSB
SBV
SSB
• ISP Communication Management
• User Call Management
• Flash Memory Management
The purpose of this process is to manage the communication and its protocol between the
on-chip bootloader and a external device. The on-chip ROM implements a serial protocol
(see section
communication frame (UART) into Flash memory access (read, write, erase, etc.).
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interface (API calls), included in the ROM bootloader. The programming
functions are selected by setting up the microcontroller’s registers before making a call to a
common entry point (0xFFF0). Results are returned in the registers. The purpose on this
process is to translate the registers values into internal Flash Memory Management. See
Application Programming (IAP)” on page 192
This process manages low level access to Flash memory (performs read and write access).
Figure
24-7, the on-chip bootloader processes are:
list some acronyms used by the Bootloader.
Definition
Boot Status Byte
Hardware Byte/Hardware Security Byte
Software Boot Vector
Software Security Byte
“Bootloader Protocol Description” on page
Bootloader
AT89LP51RD2/ED2/ID2 Preliminary
206). This process translate serial
Flash Memory
201
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