AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 27
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AT89LP51ED2
Manufacturer Part Number
AT89LP51ED2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51ED2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
2.25
Eeprom (bytes)
4096
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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4. Special Function Registers
Table 4-1.
Notes:
3714A–MICRO–7/11
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
0F8H
0F0H
98H
90H
88H
80H
1. All SFRs in the left-most column are bit-addressable.
2. Reset value is 1111 1111B when Tristate-Port Fuse is enabled and 0000 0000B when disabled.
3. Reset value is 0101 0010B when Compatibility mode is enabled and 0000 0000B when disabled.
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111
0000 0000
1111 1111
0000 0000
1111 1111
00x0 0000
xx00 0000
0x00 0000
T2CON
CCON
SCON
TCON
PSW
IEN0
ACC
IPL0
P4
P3
P2
P1
P0
B
8
0
Atmel AT89LP51RD2/ED2/ID2 SFR Map and Reset Values
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0010 0100
0000 0000
0000 0111
00xx x000
xxxx 0000
xxxx 0000
0000 xxxx
xxxx xxxx
T2MOD
SADDR
TCONB
SADEN
CMOD
TMOD
FCON
DPCF
SBUF
IEN1
CH
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect. User software should not write to these unlisted
locations, since they may be used in future products to invoke new features.
CL
AX
SP
9
1
4-1.
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
x000 0000
0000 00x0
xxxx 0000
xxxx xxx0
CCAPM0
0000 000
CCAP0H
CCAP0L
RCAP2L
EECON
BMSEL
AUXR1
DSPR
IPL1
BRL
DPL
RL0
TL0
A
2
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0100
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
x000 0000
xxxx 0000
xxx0 0000
BDRCON
CCAP1H
CCAPM1
RCAP2H
CCAP1L
SPCON
SSCON
ACSRB
ACSRA
FIRD
IPH1
DPH
RL1
TL1
B
3
AT89LP51RD2/ED2/ID2 Preliminary
0000 0000
0000 0000
0000 0000
0000 0000
x000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1000
0000 0000
CCAPM2
0000 000
CCAP2H
CCAP2L
SPSTA
DADC
MACL
DADL
SSCS
DPLB
KBLS
RH0
TH0
TL2
C
4
0000 0000
0000 0000
0000 0000
0000 0000
x000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
xxxx xxxx
xxxx xxx0
CCAPM3
CCAP3H
CCAP3L
CKSEL
SPDAT
SSDAT
MACH
DPHB
AREF
DADH
DADI
RH1
KBE
TH2
TH1
D
5
(write-only)
0000 0000
0000 0000
0000 0000
0000 0000
1111 1110
0000 0000
x000 0000
0101 xxxx
xxxx x001
WDTRST
OSCCON
CCAPM4
CCAP4H
CLKREG
CCAP4L
SSADR
AUXR
PAGE
P0M0
P1M0
P2M0
P3M0
P4M0
KBF
(2)
(2)
(2)
(2)
(2)
E
6
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
0000 0000
000x 0000
xx00 0000
0000 0xx0
xxxx x000
WDTPRG
xxxx xxx0
CKCON1
CKCON0
KBMOD
PCON
CKRL
P0M1
P1M1
P2M1
P3M1
P4M1
IPH0
SPX
BX
F
7
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
27
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