AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 101

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 15-6.
3714A–MICRO–7/11
CCAPM0 Address = 0DAH
CCAPM1 Address = 0DBH
CCAPM2 Address = 0DCH
CCAPM3 Address = 0DDH
CCAPM4 Address = 0DEH
Not Bit Addressable
Bit
Symbol
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Function
Enable Comparator
Clear to disable the comparator function of Module n. Set to enable the comparator function of Module n
Capture Positive
Clear to disable positive edge capture for Module n. Set to enable positive edge capture for Module n.
Capture Negative
Clear to disable negative edge capture for Module n. Set to enable negative edge capture for Module n.
Match Enable
When MATn = 1 and ECOMn = 1 a match between the PCA counter and Module n’s compare/capture register will set the
CCFn bit in CCON. Clear MATn to disable setting of CCFn by compare events.
Toggle Output
When TOGn = 1 and ECOMn = 1 a match between the PCA counter and Module n’s compare/capture register will toggle
the CEXn pin. Clear TOGn to disable toggling of CEXn by compare events.
Pulse Width Modulation Enable
Set to configure Module n in PWM mode and use CEXn as a PWM output. Clear to disable PWM mode for Module n.
Enable CCFn Interrupt
Clear to disable the CCFn bit in CCON as an interrupt source. Set to enable the CCFn bit in CCON to generate interrupts.
–
7
CCAPMn – PCA Module n Compare/Capture Control Register (n = 0–4)
ECOMn
Table 15-6
6
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
toggle when there is a match between the PCA counter and the modules capture/compare
register.
set when there is a match between the PCA counter and the modules capture/compare
register.
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
CAPPn
shows the CCAPMn settings for the various PCA functions.
5
CAPNn
4
AT89LP51RD2/ED2/ID2 Preliminary
MATn
3
TOGn
2
Reset Value = x000 0000B
PWMn
1
ECCFn
0
101