AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 134

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

18.6
Table 18-3.
Notes:
134
SPCON Address = C3H
Not Bit Addressable
Symbol
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit
Registers
1. Set up the clock mode before enabling the SPI: set all bits needed in SPCON except the SPEN bit, then set SPEN.
2. Enable the master SPI prior to the slave device.
3. Slave echoes master on the next Tx if not loaded with new data.
AT89LP51RD2/ED2/ID2 Preliminary
SPR2
Function
Serial Peripheral Clock Rate 2
See the description for SPR
Serial peripheral Enable
SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7. SPI = 0
disables the SPI channel.
Slave Select Disable
If SSDIS = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSDIS = 1, the SPI ignores SS in
slave mode and is active whenever SPE (SPCON.6) is set. When MSTR = 1 and SSDIS = 0, SS is monitored for master
mode collisions. Setting SSDIS = 1 will ignore collisions on SS. P1.4 may be used as a regular I/O pin when SSIG = 1.
Master/Slave Select
MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.
Clock Polarity
When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not transmitting. Please
refer to figure on SPI clock phase and polarity control.
Clock Phase
The CPHA bit together with the CPOL bit controls the clock and data relationship between master and slave. Please refer
to figure on SPI clock phase and polarity control.
Serial Peripheral Clock Rate
These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The
relationship between SCK and the oscillator frequency, F
SPR2
7
SPCON – SPI Control Register
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPEN
6
SPR0
0
1
0
1
0
1
0
1
SCK (TSCK = 0)
f
f
f
f
f
f
f
Timer 1 Overflow/2
1-0
PERIPH
PERIPH
PERIPH
PERIPH
PERIPH
PERIPH
PERIPH
SSDIS
5
/2
/4
/8
/16
/32
/64
/128
MSTR
4
OSC.
CPOL
, is as follows:
3
CPHA
2
Reset Value = 0001 0100B
SPR1
1
SPR0
3714A–MICRO–7/11
0