AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 158

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 19-10. Miscellaneous States
19.6.6
158
Status
Code
(SSCS)
F8h
00h
AT89LP51RD2/ED2/ID2 Preliminary
Combining Several TWI Modes
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface hardware
No relevant state
information available; SI =
“0”
Bus error due to an illegal
START or STOP condition
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, SI is set. To recover from a bus error, the STO
flag must set and SI must be cleared. This causes the TWI to enter the not addressed Slave
mode and to clear the STO flag (no other bits in SSCON are affected). The SDA and SCL lines
are released, and no STOP condition is transmitted.
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomic operation. If this principle is violated in a multi-master sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 19-15. Combining Several TWI Modes to Access a Serial EEPROM
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
S
S = START
To/from SSDAT
No action
No action
Transmitted from master to slave
SLA+W
Application Software Response
A
STA
0
Master Transmitter
ADDRESS
STO
1
To SSCON
No action
SI
1
A
Rs = REPEATED START
Rs
Transmitted from slave to master
AA
X
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the
bus is released and STO is cleared.
SLA+R
A
Master Receiver
DATA
3714A–MICRO–7/11
P = STOP
A
P