AT89LP51ID2 Atmel Corporation, AT89LP51ID2 Datasheet - Page 152

• Manufacturer Part Number: AT89LP51ID2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ID2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Figure 19-12. Format and States in Master Receiver Mode
19.6.3
152
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
AT89LP51RD2/ED2/ID2 Preliminary
Slave Receiver Mode
From master to slave
From slave to master
08h
S
SLA
In the Slave Receiver mode, a number of data bytes are received from a master transmitter. To
initiate the Slave Receiver mode, SSADR and SSCON must be initialized as follows:
The upper seven bits are the address to which the Two-wire Serial Interface will respond when
addressed by a master. If the LSB is set, the TWI will respond to the general call address (00h),
otherwise it will ignore the general call address.:
SSADR
Value
SSCON
Value
R
MR
CR2
S6
A or A
DATA
X
40h
48h
38h
68h
A
A
A
78h
Other master
Other master
SSIE
SA5
n
continues
continues
1
P
B0h
DATA
A
SA4
Device’s own Slave Address
STA
0
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
STO
SA3
50h
38h
To corresponding
states in slave mode
0
A
A
Other master
DATA
continues
SA2
SI
0
58h
A
SA1
AA
1
10h
P
R
S
SA0
CR1
X
SLA
3714A–MICRO–7/11
CR0
GC
X
X
W
R
MT