AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 118

• Manufacturer Part Number: AT90PWM1
• Manufacturer: Atmel Corporation

Specifications of AT90PWM1

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Table 32. Waveform Generation Mode Bit Description
Note:
15.10.2
118
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
AT90PWM1
WGMn3
Timer/Counter1 Control Register B – TCCR1B
location of these bits are compatible with previous versions of the timer.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WGMn2
(CTCn)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Note:
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes.
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
Bit
Read/Write
Initial Value
(PWMn1)
WGMn1
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
“Phase Correct PWM Mode” on page 111.
ICNC1
R/W
7
0
(PWMn0)
WGMn0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ICES1
R/W
6
0
(1)
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and Frequency
Correct
PWM, Phase and Frequency
Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
Table
R
5
–
0
32. Modes of operation supported by the Timer/Counter
WGM13
(See “16-bit Timer/Counter1 with PWM” on page
R/W
4
0
WGM
for more details.
WGM12
R/W
n2:0 definitions. However, the functionality and
3
0
TOP
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
ICRn
OCRnA
ICRn
OCRnA
ICRn
–
ICRn
OCRnA
CS12
R/W
2
0
CS11
R/W
Update of
OCRn
Immediate
TOP
TOP
TOP
Immediate
TOP
TOP
TOP
BOTTOM
BOTTOM
TOP
TOP
Immediate
–
TOP
TOP
1
0
x
at
CS10
R/W
0
0
4378C–AVR–09/08
TOVn Flag
Set on
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
–
TOP
TOP
TCCR1B
96.).
See