AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 17

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AT90PWM1

Manufacturer Part Number
AT90PWM1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT90PWM1

Flash (kbytes)
8 Kbytes
Pin Count
24
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
19
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
1
Pwm Channels
7
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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6. Memories
6.1
6.2
4378C–AVR–09/08
In-System Reprogrammable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the AT90PWM1. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
AT90PWM1 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
The AT90PWM1 contains 8K bytes On-chip In-System Reprogrammable Flash memory for pro-
gram storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x
16. For software security, the Flash Program memory space is divided into two sections, Boot
Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM1
Program Counter (PC) is 12 bits wide, thus addressing the 4K program memory locations. The
operation of Boot Program section and associated Boot Lock bits for software protection are
described in detail in
205.
in SPI or Parallel programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory.
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 1. Program Memory Map
Figure 2
“Memory Programming” on page 219
shows how the AT90PWM1 SRAM Memory is organized.
13.
“Boot Loader Support – Read-While-Write Self-Programming” on page
Application Flash Section
Boot Flash Section
Program Memory
contains a detailed description on Flash programming
0x0000
0x0FFF
“Instruction Execution Tim-
AT90PWM1
17

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