AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 143
AT90PWM1
Manufacturer Part Number
AT90PWM1
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM1
Flash (kbytes)
8 Kbytes
Pin Count
24
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
19
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
1
Pwm Channels
7
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM1-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT90PWM161-16MN
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT90PWM161-WN
Manufacturer:
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Quantity:
20 000
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16.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
4378C–AVR–09/08
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
PSCOUTn0
PSCOUTn1
PSC Input A
PSC Input B
DT0
DT0
OT0
OT0
Figure 16-22. PSCn behaviour versus PSCn Input A in Fault Mode 2
PSC Input A is take into account during DT0 and OT0 only. It has no effect during DT1 and OT1.
When PSCn Input A event occurs, PSC releases PSCOUTn0, jumps and executes DT1 plus
OT1 and then waits for PSC Input A inactive state.
Even if PSC Input A is released during DT1 or OT1, DT1 plus OT1 sub-cycle is always com-
pletely executed.
Figure 16-23. PSCn behaviour versus PSCn Input B in Fault Mode 2
PSC Input B is take into account during DT1 and OT1 only. It has no effect during DT0 and OT0.
When PSC Input B event occurs, PSC releases PSCOUTn1, jumps and executes DT0 plus OT0
and then waits for PSC Input B inactive state.
Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com-
pletely executed.
DT1
DT1
OT1
OT1
DT0
DT0 OT0 DT1
OT0
DT1
OT1
OT1
DT0
OT0
DT0
OT0
AT90PWM1
DT1
DT1
OT1
OT1
143
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