AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 178

• Manufacturer Part Number: AT90PWM2B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM2B

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.2.2
17.2.3
17.2.4
178
AT90PWM2/3/2B/3B
Master Mode
MCU Control Register – MCUCR
SPI Control Register – SPCR
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin
is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
mode.
• Bit 7– SPIPS: SPI Pin Redirection
Thanks to SPIPS (SPI Pin Select) in MCUCR Sfr, SPI pins can be redirected.
On 32 pins packages, SPIPS has the following action:
On 24 pins package, SPIPS has the following action:
Note that programming port are always located on alternate SPI port.
Bit
Bit
Read/Write
Initial Value
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
set, the interrupt routine will be executed.
–
–
–
–
When the SPIPS bit is written to zero, the SPI signals are directed on pins
MISO,MOSI, SCK and SS.
When the SPIPS bit is written to one,the SPI signals are directed on alternate SPI
pins, MISO_A, MOSI_A, SCK_A and SS_A.
When the SPIPS bit is written to zero, the SPI signals are directed on alternate SPI
pins, MISO_A, MOSI_A, SCK_A and SS_A.
When the SPIPS bit is written to one,the SPI signals are directed on pins
MISO,MOSI, SCK and SS.
SPIPS
SPIE
R/W
7
7
0
SPE
6
R
6
–
0
DORD
5
R
5
–
0
MSTR
PUD
R/W
4
4
0
CPOL
3
R
3
–
0
CPHA
2
R
2
–
0
SPR1
IVSEL
R/W
1
1
0
SPR0
IVCE
R/W
0
0
0
4317J–AVR–08/10
MCUCR
SPCR