AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 248

• Manufacturer Part Number: AT90PWM2B
• Manufacturer: Atmel Corporation

Specifications of AT90PWM2B

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.8.3
248
AT90PWM2/3/2B/3B
ADC Control and Status Register B– ADCSRB
In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB register.
See
• Bit 4– ADIF: ADC Interrupt Flag
Set by hardware as soon as a conversion is complete and the Data register are updated with the
conversion result.
Cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF can be cleared by writing it to logical one.
• Bit 3– ADIE: ADC Interrupt Enable Bit
Set this bit to activate the ADC end of conversion interrupt.
Clear it to disable the ADC end of conversion interrupt.
• Bit 2, 1, 0– ADPS2, ADPS1, ADPS0: ADC Prescaler Selection Bits
These 3 bits determine the division factor between the system clock frequency and input clock of
the ADC.
The different setting are shown in
Table 21-5.
Bit
Read/Write
Initial Value
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. Set this bit if you wish to convert with
an ADC clock frequency higher than 200KHz.
• Bit 4– ADASCR: Analog to Digital Conversion on Amplified Channel Start Conversion
Set this to request a conversion on an amplified channel.
Cleared by hardware as soon as the Analog to Digital Conversion is started.
Alternatively, this bit can be cleared by writing it to logical zero.
In order to start a conversion on an amplified channel with the AT90PWM2B/3B, use the ADCS
bit in ADCSRA register.
• Bit 3, 2, 1, 0– ADTS3:ADTS0: ADC Auto Trigger Source Selection Bits
These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE
bit in ADCSRA register is set.
ADPS2
0
0
0
0
1
1
1
1
Request Bit (AT90PWM2/3 only - NA on AT90PWM2B/3B)
Table 21-6 on page
ADC Prescaler Selection
ADPS1
0
0
1
1
0
0
1
1
ADHSM
7
0
-
249.
6
0
-
-
ADPS0
0
1
0
1
0
1
0
1
Table
5
0
-
-
21-5.
ADASCR
Division Factor
2
2
4
8
16
32
64
128
R/W
4
0
ADTS3
R/W
3
0
ADTS2
R/W
2
0
ADTS1
R/W
1
0
ADTS0
R/W
0
0
4317J–AVR–08/10
ADCSRB