ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 170

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

18.4
18.4.1
2549N–AVR–05/11
Register Description
GTCCR – General Timer/Counter Control Register
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 18-2. Prescaler for synchronous Timer/Counters
Bit
0x23 (0x43)
Read/Write
Initial Value
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
PSR10
clk
CSn0
CSn1
CSn2
Tn
Tn
I/O
Synchronization
Synchronization
TSM
R/W
7
0
ExtClk
R
6
–
0
< f
TIMER/COUNTERn CLOCK SOURCE
clk_I/O
ATmega640/1280/1281/2560/2561
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
clk
Clear
Tn
R
4
–
0
R
3
–
0
CSn0
CSn1
CSn2
R
2
–
0
TIMER/COUNTERn CLOCK SOURCE
PSRASY PSRSYNC
R/W
1
0
clk
Tn
R/W
clk_I/O
0
0
/2.5.
GTCCR
170