ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 48
ATmega1281R231
Manufacturer Part Number
ATmega1281R231
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1281R231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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10.9
2549N–AVR–05/11
External Clock
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 10-12. Start-up Times for the 128kHz Internal Oscillator
To drive the device from an external clock source, XTAL1 should be driven as shown in
10-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 10-4. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 10-15 on page
Table 10-13. Crystal Oscillator Clock Frequency
Table 10-14. Start-up Times for the External Clock Selection
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Slowly rising power
Slowly rising power
Power Conditions
Power Conditions
Fast rising power
Fast rising power
10-12.
BOD enabled
BOD enabled
Nominal Frequency
51.
0 - 16MHz
EXTERNAL
Start-up Time from Power-
Start-up Time from Power-
SIGNAL
CLOCK
down and Power-save
down and Power-save
ATmega640/1280/1281/2560/2561
NC
Reserved
Reserved
6CK
6CK
6CK
6CK
6CK
6CK
XTAL2
XTAL1
GND
Additional Delay from
Additional Delay from
Reset (V
14CK + 4.1ms
14CK + 64ms
14CK + 65ms
14CK + 4ms
Reset
14CK
14CK
CC
CKSEL3:0
= 5.0V)
0000
SUT1:0
SUT1:0
00
01
10
11
Figure
00
01
10
11
48
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