ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 244

• Manufacturer Part Number: ATmega1281R231
• Manufacturer: Atmel Corporation

Specifications of ATmega1281R231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 54
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

24.3.4
24.3.5
Figure 24-6. Typical Data Transmission
2549N–AVR–05/11
SDA
SCL
START
Data Packet Format
Combining Address and Data Packets into a Transmission
Addr MSB
1
2
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 24-5. Data Packet Format
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 24-6
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
SLA+R/W
Aggregate
Transmitter
SDA from
SDA from
SCL from
Receiver
Master
SDA
Addr LSB
SLA+R/W
7
shows a typical data transmission. Note that several data bytes can be transmitted
R/W
8
ACK
Data MSB
9
1
ATmega640/1280/1281/2560/2561
2
Data MSB
1
Data Byte
7
2
Data Byte
Data LSB
8
7
ACK
9
Data LSB
8
ACK
9
STOP, REPEATED
START or Next
Data Byte
STOP
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