ATmega1281R231 Atmel Corporation, ATmega1281R231 Datasheet - Page 308
ATmega1281R231
Manufacturer Part Number
ATmega1281R231
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1281R231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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28.6
28.6.1
28.6.2
28.7
28.8
2549N–AVR–05/11
Boundary-scan Related Register in I/O Memory
ATmega640/1280/1281/2560/2561 Boundary-scan Order
Boundary-scan Description Language Files
MCUCR – MCU Control Register
MCUSR – MCU Status Register
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
Table 28-1 on page 309
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and
Port K is scanned in the opposite bit order of the other ports. Exceptions from the rules are the
Scan chains for the analog circuits, which constitute the most significant bits of the scan chain
regardless of which physical pin they are connected to. In
corresponds to FF0, PXn. Control corresponds to FF1, PXn. Bit 4, bit 5, bit 6 and bit 7 of Port F
is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATmega1281/2561 and ATmega640/1280/2560.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x34 (0x54)
Read/Write
Initial Value
R/W
JTD
7
0
7
–
R
0
shows the Scan order between TDI and TDO when the Boundary-scan
R
R
6
–
0
6
–
0
ATmega640/1280/1281/2560/2561
R
R
5
–
0
5
–
0
JTRF
PUD
R/W
R/W
4
0
4
WDRF
R/W
R
3
–
0
3
See Bit Description
Figure 28-3 on page
BORF
R/W
R
2
–
0
2
EXTRF
IVSEL
R/W
R/W
1
0
1
PORF
IVCE
306, PXn. Data
R/W
R/W
0
0
0
MCUCR
MCUSR
308
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