ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 109

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ATmega32C1 Automotive

Manufacturer Part Number
ATmega32C1 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega32C1 Automotive

Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
13.1.2
13.2
7647G–AVR–09/11
Accessing 16-bit Registers
Definitions
The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Coun-
ter value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OCnx).
put Compare Units” on page 116.
Flag (OCFnx) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge
triggered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digi-
tal filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be
defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When
using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for gener-
ating a PWM output. However, the TOP value will in this case be double buffered allowing the
TOP value to be changed in run time. If a fixed TOP value is required, the ICRn Register can
be used as an alternative, freeing the OCRnA to be used as PWM output.
The following definitions are used extensively throughout the section:
The TCNTn, OCRnx, and ICRn are 16-bit registers that can be accessed by the AVR CPU via
the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera-
tions. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the
16-bit access. The same temporary register is shared between all 16-bit registers within each
16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low
byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register,
and the low byte written are both copied into the 16-bit register in the same clock cycle. When
the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is cop-
ied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnx
16-bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the
low byte must be read before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for access-
ing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit
access.
BOTTOM
MAX
TOP
The counter reaches the BOTTOM when it becomes 0x0000.
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF,
0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assign-
ment is dependent of the mode of operation.
The compare match event will also set the Compare Match
Atmel ATmega16/32/64/M1/C1
See “Out-
109

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