ATmega32C1 Automotive Atmel Corporation, ATmega32C1 Automotive Datasheet - Page 193

• Manufacturer Part Number: ATmega32C1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega32C1 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.10.9
7647G–AVR–09/11
CAN Bit Timing Register 2 - CANBT2
• Bit 6:1 – BRP5:0: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the indi-
vidual bit timing.
If ‘BRP[5..0]=0’, see
Sample Point(s)” on page
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT1 is written.
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT2 is written.
• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the con-
troller must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period
may be shortened or lengthened by a re-synchronization.
• Bit 4 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT2 is written.
• Bit 3:1 – PRS2:0: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network.
It is twice the sum of the signal propagation time on the bus line, the input comparator delay
and the output driver delay.
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT2 is written.
Tscl
Tsjw
Tprs
Initial Value
Read/Write
=
=
=
Bit
-------------------------------------- -
clk
Tscl
Tscl
BRP[5:0]
IO
frequency
PRS[2:0]
SJW[1:0]
+
7
-
-
-
1
Section 16.4.3 “Baud Rate” on page 177
+
+
SJW1
1
R/W
1
6
0
194.
SJW0
R/W
5
0
Atmel ATmega16/32/64/M1/C1
4
-
-
-
PRS2
R/W
3
0
PRS1
R/W
2
0
and
PRS0
R/W
Section • “Bit 0 – SMP:
1
0
0
-
-
-
CANBT2
193