ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 272

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

22.12.2
22.13 OUT endpoint management
22.13.1
7766F–AVR–11/10
Control Read
Overview
The next figure shows a control read transaction. The USB controller has to manage the simulta-
neous write requests from the CPU and the USB host:
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data written by the CPU are erased, and
clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request have priority over any other request and has to be ACK’ed. This means that
any other flag should be cleared and the fifo reset when a SETUP is received.
WARNING: the byte counter is reset when the OUT Zero Length Packet is received. The firm-
ware has to take care of this.
OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or
not the bank when it is empty.
The Endpoint must be configured first.
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-
rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
USB line
RXSTPI
RXOUTI
TXINI
Wr Enable
HOST
Wr Enable
CPU
SETUP
SETUP
HW
SW
SW
IN
HW
DATA
SW
IN
ATmega16/32U4
OUT
NAK
STATUS
OUT
HW
SW
272