ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 28
ATmega32U4
Manufacturer Part Number
ATmega32U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.2
7766F–AVR–11/10
Clock Sources
ADC Clock – clk
PLL Prescaler Clock – clk
PLL Output Clock – clk
High-Speed Timer Clock– clk
USB Clock – clk
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The PLL requires a 8 MHz input. A prescaler allows user to use either a 8MHz or a 16MHz
source (from a crystal or an external source), using a divider (by 2) if necessary. The output of
the prescaler goes into the PLL Input multiplexer, that allows the user to select either the pres-
caler output of the System Clock Multiplexer, or the Internal 8MHz Calibrated Oscillator.
When enabled, the PLL outputs one frequency among numerous choices between 32MHz and
96 MHz. The output frequency is determined by the PLL clock register. The frequency is inde-
pendent of the power supply voltage. The PLL Output is connected to a postcaler that allows
user to generate two different frequencies (clk
each on them resulting of a selected division ratio (/1, /1.5, /2).
When enabled, the PLL outputs one frequency among numerous choices between 32MHz and
96 MHz, that goes into the PLL Postcaler. The High Speed Timer frequency input is generated
from the PLL Postcaler, that proposes /1, /1.5 and /2 ratios. That can be determined from the
PLL clock register. The High Speed Timer maximum frequency input depends on the power sup-
ply voltage and reaches its maximum of 64 MHz at 5V.
The USB hardware module needs for a 48 MHz clock. This clock is generated from the on-chip
PLL. The output of the PLL passes through the PLL Postcaler where the frequency can be either
divided by 2 or directly connected to the clk
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
USB
ADC
Device Clocking Option
Low Power Crystal Oscillator
Reserved
Low Frequency Crystal Oscillator
Reserved
Calibrated Internal RC Oscillator
External Clock
Reserved
1. For all fuses “1” means unprogrammed while “0” means programmed.
Pll
PllPresc
Device Clocking Options Select
TMR
USB
(1)
signal.
USB
and clk
TMR
) from the common PLL signal,
ATmega16/32U4
(or EXCKSEL[3:0])
1111 - 1000
0101 - 0100
CKSEL[3:0]
0111 - 0110
0011
0010
0000
0001
28
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