ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 87

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.0.3
11.0.4
11.0.5
11.0.6
7766F–AVR–11/10
External Interrupt Mask Register – EIMSK
External Interrupt Flag Register – EIFR
Pin Change Interrupt Control Register - PCICR
Pin Change Interrupt Flag Register – PCIFR
• Bit 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bits 7..0 – INT6, INT3 – INT0: External Interrupt Request 6, 3 - 0 Enable
When an INT[6;3:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one),
the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the Exter-
nal Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is
activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an
interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
• Bits 7..0 – INTF6, INTF3 - INTF0: External Interrupt Flags 6, 3 - 0
When an edge or logic change on the INT[6;3:0] pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT[6;3:0] in
EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
These flags are always cleared when INT[6;3:0] are configured as level interrupt. Note that when
entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be
disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See
“Digital Input Enable and Sleep Modes” on page 69
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt
Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
-
R/W
0
7
-
R/W
0
7
R
0
7
R
0
6
INT6
R/W
0
6
INTF6
R/W
0
6
R
0
6
R
0
5
-
R/W
0
5
-
R/W
0
5
–
R
0
5
–
R
0
4
-
R/W
0
4
-
R/W
0
4
–
R
0
4
–
R
0
3
INT3
0
3
INTF3
0
R/W
R/W
3
–
R
0
3
–
R
0
for more information.
2
INT2
R/W
0
2
INTF2
R/W
0
2
–
R
0
2
–
R
0
1
INT1
R/W
0
1
INTF1
R/W
0
1
–
R
0
1
–
R
0
ATmega16/32U4
0
IINT0
R/W
0
0
IINTF0
R/W
0
0
PCIE0
R/W
0
0
PCIF0
R/W
0
EIMSK
EIFR
PCICR
PCIFR
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