ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 170
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Quantity
Price
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14.12.9
8077H–AVR–12/09
CTRLGCLR/CTRLGSET - Control Register G Clear/Set
• Bit 3:2 - CMD[1:0]: Timer/Counter Command
These command bits can be used for software control of update, restart, and reset of the
Timer/Counter. The command bits are always read as zero.
Table 14-7.
• Bit 1 - LUPD: Lock Update:
When this bit is set no update of the buffered registers is performed, even though an UPDATE
condition has occurred. Locking the update ensures that all buffers, including DTI buffers, are
valid before an update is performed.
This bit has no effect when input capture operation is enabled.
• Bit 0 - DIR: Counter Direction:
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that
the counter is in down counting (decrementing) state.
Normally this bit is controlled in hardware by the waveform generation mode, or by event
actions, but this bit can also be changed from software.
Refer to section
mation on how to access this type of status register.
• Bit 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:1 - CCxBV: Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding CCxBUF register. These
bits are automatically cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on capture event and cleared if the
corresponding CCxIF is cleared.
• Bit 0 - PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically
cleared on an UPDATE condition.
Bit
+0x0A/ +0x0B
Read/Write
Initial Value
CMD
00
01
10
11
Command selections
7
R
0
-
”CTRLFCLR/CTRLFSET - Control Register F Clear/Set” on page 169
Group Configuration
RESTART
R
6
0
-
UPDATE
RESET
NONE
R
5
0
-
CCDBV
R/W
4
0
Command Action
None
Force Update
Force Restart
Force Hard Reset (Ignored if T/C is not in “OFF“state)
CCCBV
R/W
3
0
CCBBV
R/W
2
0
CCABV
R/W
1
0
PERBV
R/W
XMEGA A
0
0
CTRLGCLR/SET
for infor-
170
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