ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 32
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3-MH
Manufacturer:
ZARLINK
Quantity:
101
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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4.16.5
8077H–AVR–12/09
FUSEBYTE5 - Non-Volatile Memory Fuse Byte 5
Table 4-3.
• Bit 1 - WDLOCK: Watchdog Timer lock
The WDLOCK fuse can be programmed to lock the Watchdog Timer configuration. When this
fuse is programmed the Watchdog Timer configuration cannot be changed, and the Watchdog
Timer cannot be disabled from the application software. When this fuse is programmed the
ENABLE bit in the watchdog CTRL register is automatically set at reset. The WEN bit in the
watchdog WINCTRL register is not set automatically and needs to be enabled from software.
Table 4-4.
• Bit 0 - JTAGEN: JTAG enabled
The JTAGEN fuse decides whether or not the JTAG interface is enabled.
When the JTAG interface is disabled all access through JTAG is prohibited, and the device can
only be accessed using the Program and Debug Interface (PDI).
Table 4-5.
The JTAGEN fuse is only available on devices with JTAG interface.
• Bit 7:6 - Reserved
These bits are reserved. For compatibility with future devices, always write these bits to one
when this register is written.
Bit
+0x05
Read/Write
Initial Value
STARTUPTIME[1:0]
WDLOCK
JTAGEN
00
01
10
11
0
1
0
1
Start-up Time
Watchdog Timer locking
JTAG Enable
R/W
7
1
-
Description
Watchdog Timer locked for modifications
Watchdog Timer not locked
Description
JTAG enabled
JTAG disabled
R/W
6
1
-
R
5
BODACT[1:0]
-
4
R
-
1kHz ULP oscillator Cycles
EESAVE
R/W
3
-
Reserved
64
4
0
R/W
2
-
BODLEVEL[2:0]
R/W
1
-
XMEGA A
R/W
0
-
FUSEBYTE5
32
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