ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 302
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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25.16 Register Description - ADC
25.16.1
25.16.2
8077H–AVR–12/09
CTRLA - ADC Control Register A
CTRLB - ADC Control Register B
• Bits 7:6 – DMASEL[1:0]: DMA Request Selection
In addition to giving DMA transfer request for each ADC channel, the ADC can be set up to give
a combined request for all channels. The combined request is decided according to the DMA-
SEL bits. See
Table 25-1.
• Bits 5:2 – CH[3:0]START: ADC Channel Start single conversion
Setting any of these bits will start a conversion on the corresponding ADC channel. Setting sev-
eral bits at the same time will start a conversion sweep on the selected ADC channels, starting
with the channel with lowest number. These bits are cleared by hardware when the conversion
has started.
• Bit 1 – FLUSH: ADC Pipeline Flush:
Setting this bit will flush the ADC pipeline. When this is done the ADC Clock will be restarted on
the next Peripheral clock edge and all conversions in progress are aborted and lost.
After the flush and the ADC Clock restart, the ADC will resume where it left off. I.e. if a channel
sweep was in progress or any conversions was pending, these will enter the ADC pipeline and
complete.
• Bit 0 – ENABLE: ADC Enable
Setting this bit enables the ADC.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
DMASEL[1:0]
00
01
10
11
R/W
7
R
0
-
7
0
Table 25-1
ADC DMA Request Selection
DMASEL[1:0]
R
R/W
6
0
-
6
0
for details.
Group Configuration
R
5
0
R/W
-
5
0
CH0123
CH012
CH01
CONVMODE
OFF
R/W
R/W
4
0
4
0
CH[3:0]START
FREERUN
R/W
R/W
3
0
3
0
Description
No combined DMA request
ADC Channel 0 or 1
ADC Channel 0 or 1 or 2
ADC Channel 0 or 1 or 2 or 3
R/W
R/W
RESOLUTION[1:0]
2
0
2
0
FLUSH
R/W
R/W
1
0
1
0
XMEGA A
ENABLE
R/W
R
0
0
0
0
-
CTRLA
CTRLB
302
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