ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 33
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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4.16.6
8077H–AVR–12/09
LOCKBITS - Non-Volatile Memory Lock Bit Register
• Bit 5:4 - BODACT[1:0]: BOD operation in active mode
The BODACT fuse bits set the BOD operation mode when the device is in active and idle mode
of operation. For details on the BOD and BOD operation modes refer to
Out Detection” on page
Table 4-6.
• Bit 3 - EESAVE: EEPROM memory is preserved through the Chip Erase
A chip erase command will normally erase the Flash, EEPROM and internal SRAM. If the
EESAVE fuse is programmed, the EEPROM is not erased during chip erase. In case EEPROM
is used to store data independent of software revision, the EEPROM can be preserved through
chip erase.
Table 4-7.
Changing of the EESAVE fuse bit takes effect immediately after the write time-out elapses.
Hence, it is possible to update EESAVE and perform a chip erase according to the new setting
of EESAVE without leaving and re-entering programming mode
• Bit 2:0 - BODLEVEL[2:0] - Brown out detection voltage level
The BODLEVEL fuse bits sets the nominal BOD level value. During power-on the device is kept
in reset until the V
that the BOD level is set lower than the V
normal operation, refer to
nominal values, see
• Bit 7:6 - BLBB[1:0]: Boot Lock Bit Boot Loader Section
These bits indicate the locking mode for the Boot Loader Section. Even though the BLBB bits
are writable, they can only be written to a stricter locking. Resetting the BLBB bits is only possi-
ble by executing a Chip Erase Command.
Bit
+0x07
Read/Write
Initial Value
BODACT[1:0]
EESAVE
00
01
10
11
0
1
BOD operation modes in Active and Idle mode
EEPROM memory through Chip Erase
R/W
7
1
Description
Reserved
BOD enabled in sampled mode
BOD enabled continuously
BOD Disabled
Description
EEPROM is preserved during chip erase
EEPROM is not preserved during chip erase
CC
BLBB[1:0]
Table 9-2 on page
level has reached the programmed BOD level. Due to this always ensure
106.
R/W
6
1
Section 9.4 ”Reset Sources” on page 104
R/W
5
1
BLBA[1:0]
106.
CC
R/W
level, also if the BOD is not enabled and used during
4
1
R/W
3
1
BLBAT[1:0]
R/W
2
1
R/W
for details. For BOD level
1
1
LB[1:0]
Section 9.4.2 ”Brown-
XMEGA A
R/W
0
1
LOCKBITS
33
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