ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 298
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3-MH
Manufacturer:
ZARLINK
Quantity:
101
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
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Quantity:
1
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25.9.3
25.9.4
8077H–AVR–12/09
Single conversions on two ADC channels
Single conversions on two ADC channels, CH0 with gain
Figure 25-14. ADC timing for one single conversion with gain
Figure 25-15 on page 298
The pipelined design enables the second conversion to start on the next ADC clock cycle after t
the first conversion is started. In this example both conversions is triggered at the same time, but
for ADC Channel 1 (CH1) the actual start is not until the ADC sample and conversion of the MSB
for ADC Channel 0 (CH0) is done.
Figure 25-15. ADC timing for single conversions on two ADC channels
Figure 25-16 on page 299
nels where ADC Channel 0 uses the gain stage. As the gain stage introduce one addition cycle
for the gain sample and amplify, the sample for ADC Channel 1 is also delayed one ADC clock
cycle, until the ADC sample and MSB conversion is done for ADC Channel 0.
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
CONVERTING BIT
ADC SAMPLE
ADC SAMPLE
START CH0
START CH1
CLK
CLK
IF CH0
IF CH1
START
ADC
ADC
IF
1
1
MSB
shows the conversion timing for single conversions on two ADC chan-
10
shows the ADC timing for single conversions on two ADC channels.
2
2
MSB
MSB
9
10
10
8
3
3
9
7
9
8
6
8
4
4
7
5
7
6
4
6
5
5
5
3
5
4
2
4
6
6
3
1
3
LSB
2
2
7
7
1
1
XMEGA A
LSB
LSB
8
8
9
9
298
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