ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 326
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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ZARLINK
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101
Company:
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Manufacturer:
ATMEL
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26.10.9.1
26.10.9.2
26.10.10 CH1DATAL – DAC Channel 1 Data Register Low byte
26.10.10.1
26.10.10.2
26.10.11 GAINCAL – DAC Gain Calibration Register
8077H–AVR–12/09
Right-adjusted
Left-adjusted
Right-adjusted
Left-adjusted
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:0 - CHDATA[11:8]: DAC Conversion Data Register Channel 1, 4 MSB
These bits are the 4 MSB of the 12-bit value to convert to channel 1 in right-adjusted mode.
• Bits 7:0 - CHDATA[11:4]: DAC Conversion Data Register Channel 1, 8 MSB
These bits are the 8 MSB of the 12-bit value to convert to channel 1 in left-adjusted mode.
• Bits 7:0 - CHDATA[7:0]: DBC Conversion Data Register Channel 1, 8 LSB
These bits are the 8 lsb of the 12-bit value to convert to channel 1 in right-adjusted mode.
• Bits 7:4 - CHDATA[3:0]: DAC Conversion Data Register Channel 1, 4 LSB
These bits are the 4 lsb of the 12-bit value to convert to channel 1 in left-adjusted mode.
• Bits 3:0 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
Bit
+0x08
Read/Write
Initial Value
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
R
7
0
-
Bit
+0x1A
Read/Write
Read/Write
Initial Value
Initial Value
R/W
6
0
R/W
R/W
7
0
0
R/W
5
0
R/W
R/W
6
0
0
CHDATA[3:0]
R/W
4
0
R/W
R/W
GAINCAL[6:0]
5
0
0
R/W
3
0
R/W
R/W
4
0
0
CHDATA[7:0]
R/W
2
0
R/W
R
0
0
3
-
R/W
1
0
R/W
R
2
0
0
-
XMEGA A
R/W
0
0
R/W
R
1
0
0
-
GAINCAL
R/W
R
0
0
0
-
326
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