ATxmega16D4 Atmel Corporation, ATxmega16D4 Datasheet - Page 85
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega16D4
Manufacturer Part Number
ATxmega16D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega16D4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega16D4-AU
Manufacturer:
Atmel
Quantity:
438
Part Number:
ATxmega16D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega16D4-MH
Manufacturer:
Atmel
Quantity:
1 605
Company:
Part Number:
ATxmega16D4-MHR
Manufacturer:
SANYO
Quantity:
50
Part Number:
ATxmega16D4-MHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8.4.3
8.4.4
8210B–AVR–04/10
External reset
Watchdog reset
The BODACT fuse determines the BOD setting for active mode and idle mode, while the
BODDS fuse determines the brown-out detection setting for all sleep modes except idle mode.
Table 8-3.
The External reset circuit is connected to the external RESET pin. The external reset will trigger
when the RESET pin is driven below the RESET pin threshold voltage, V
minimum pulse period t
includes an internal pull-up resistor.
Figure 8-5.
For characterization data on V
datasheet.
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the
WDT is not reset from the software within a programmable timout period, a Watchdog reset will
be given. The Watchdog reset is active for 1-2 clock cycles on the 2 MHz internal RC oscillator.
• Sampled: In this mode the BOD circuit will sample the VCC level with a period identical to
the 1 kHz output from the Ultra Low Power (ULP) oscillator. Between each sample the BOD is
turned off. This mode will reduce the power consumption compared to the enabled mode, but
a fall in the V
If a brown-out is detected in this mode, the BOD circuit is set in enabled mode to ensure that
the device is kept in reset until V
CC
BODACT[1:0]/ BODDS[1:0]
BOD setting Fuse Decoding
External reset characteristics.
CC
level between 2 positive edges of the 1 kHz ULP output will not be detected.
EXT
00
01
10
11
t
EXT
. The reset will be held as long as the pin is kept low. The reset pin
RST
CC
and t
is above V
EXT
and pull-up resistor values consult the device
BOT
again.
Reserved
Sampled
Disabled
Enabled
Mode
RST
, for longer than the
XMEGA D
85