ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 262
ATxmega32A4
Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.4.1
8077H–AVR–12/09
Key and State Memory
The following procedure for setup and use is recommended:
If more than one block is to be encrypted or decrypted repeat the procedure from step 3.
When the encryption/decryption procedure is complete the AES Interrupt Flag is set and the
optional interrupt is generated.
The AES Key and State memory are both 16 x 8-bit memories that are accessible through the
Key (KEY) and State (STATE) register, respectively.
Each memory has two 4-bit address pointers used to address the memory for read and write,
respectively. The initial value of the pointers are zero. After a read or write operation to the State
or Key register, the appropriate pointer is automatically incremented. Accessing (read or write)
the Control Register (CTRL) will reset all pointers to zero. A pointer overflow (a sequential read
or write is done more than 16 times) will also set the affected pointer to zero. The address point-
ers are not accessible from software. Read and write memory pointers are both incremented
during write operations in XOR mode.
Access to the Key and State registers are only possible when encryption/decryption is not in
progress.
Figure 23-2. The State memory with pointers and register
1. Enable AES interrupts (optional)
2. Select the AES direction, encryption or decryption.
3. Load the Key data block into the AES Key memory
4. Load the data block into the AES State memory
5. Start the encryption/decryption operation
address pointer
4-bit state write
reset or access
Reset pointer
to AES Control
I/O Data Bus
XOR
STATE
14
15
0
1
-
xor
STATE[read pointer]
address pointer
4-bit state read
reset or access
to AES Control
Reset pointer
XMEGA A
262
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