ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 272
ATxmega32A4
Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.6.5
24.6.6
24.7
24.7.1
8077H–AVR–12/09
SRAM LPC Configuration
Address Latch Requirements
Timing
Multiplexing Data with Address Byte 0
Figure 24-5. Multiplexed SRAM connection using ALE1 and ALE2
The Address Latch timing and parameter requirements are described in
277.
SRAM or external memory devices may have different timing requirements. To meet these vary-
ing requirements, each Chip Select can be configured with different wait-states. Timing details is
described in
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing
modes where the data and address lines are multiplexed. Compared to SRAM configuration,
this can further reduce the number of pins required for the EBI. The available configurations is
shown in
Timing and Address Latch requirements is as for SRAM configuration.
When the data byte and address byte 0 (AD[7:0]) are multiplexed, they are output from the same
port, and the ALE1 signal from the device controls the address latch.
Figure 24-6. Multiplexed SRAM LPC connection using ALE1
Section 24.7.1 on page 272
”EBI Timing” on page
EBI
EBI
A[23:16]/
A[19:16]
A[15:8]/
AD[7:0]
A[15:8]
D[7:0]
A[7:0]
ALE1
ALE2
ALE1
277.
through
D
G
Q
Section 24.7.2 on page
D
G
D
G
Q
Q
D[7:0]
A[7:0]
A[15:8]
A[23:16]
D[7:0]
A[7:0]
A[15:8]
A[19:16]
273.
SRAM
SRAM
”EBI Timing” on page
XMEGA A
272
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