ATxmega32A4 Atmel Corporation, ATxmega32A4 Datasheet - Page 29
ATxmega32A4
Manufacturer Part Number
ATxmega32A4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32A4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
7
Twi (i2c)
2
Uart
5
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
16
Pwm Channels
16
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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4.15.12
8077H–AVR–12/09
LOCKBITS - Non-Volatile Memory Lock Bit Register
• Bit 5:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - EELOAD: EEPROM Page Buffer Active Loading
The EELOAD status flag indicates that the temporary EEPROM page buffer has been loaded
with one or more data bytes. Immediately after an EEPROM load command is issued and byte is
written to NVMDR, or a memory mapped EEPROM buffer load operation is performed, the
EELOAD flag is set, and it remains set until an EEPROM page write- or a page buffer flush oper-
ation is executed.
• Bit 0 - FLOAD: Flash Page Buffer Active Loading
The FLOAD flag indicates that the temporary Flash page buffer has been loaded with one or
more data bytes. Immediately after a Flash load command has been issues and byte is written to
NVMDR, the FLOAD flag is set, and it remains set until an Application- or Boot page write- or a
page buffer flush operation is executed.
This register is a direct mapping of the NVM Lockbits into the IO Memory Space, in order to
enable direct read access from the application software. Refer to
Memory Lock Bit Register” on page 34
Bit
+0x07
Read/Write
Initial Value
R
7
1
BLBB[1:0]
R
6
1
R
5
1
BLBA[1:0]
for description of the Lock Bits.
R
4
1
R
3
1
BLBAT[1:0]
2
R
1
”LOCKBITS - Non-Volatile
R
1
1
LB[1:0]
XMEGA A
R
0
1
LOCKBITS
29
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