ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 204
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ATxmega64D3
Manufacturer Part Number
ATxmega64D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA64D3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega64D3-AU
Manufacturer:
JST
Quantity:
1 000
Part Number:
ATxmega64D3-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega64D3-MH
Manufacturer:
Atmel
Quantity:
515
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18.4
8210B–AVR–04/10
Frame Formats
Leading edge is the first clock edge in a clock cycle. Trailing edge is the last clock edge in a
clock cycle.
Figure 18-4. UCPHA and INVEN data transfer timing diagrams.
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (start and stop bits), and an optional parity bit for error checking. Note that
this does not apply to SPI operation (See
30 combinations of the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit and all data bits ending
with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the first
stop bit. One frame can be directly followed by a start bit and a new frame, or the communication
line can return to idle (high) state.
of the frame formats. Bits inside brackets are optional.
Figure 18-5. Frame Formats
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
XCK
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
(IDLE)
St
0
INVEN=0
1
2
Figure 18-5 on page 204
3
Section 18.4.2 on page
4
FRAME
[5]
[6]
[7]
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
[8]
illustrates the possible combinations
[P]
205). The USART accepts all
Sp1 [Sp2]
INVEN=1
(St / IDLE)
XMEGA D
204
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