ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 234

• Manufacturer Part Number: ATxmega64D3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64D3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 200
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 18
• Input Capture Channels: 18
• Pwm Channels: 18
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.10 Interrupts and events
20.11 Calibration
20.12 Register Description - ADC
20.12.1
8210B–AVR–04/10
CTRLA - ADC Control Register A
Figure 20-18. ADC input for differential measurements and differential measurements with gain
In order to achieve n bit accuracy, the source output resistance, R
ADC input resistance on a pin:
where T
For details on R
teristic in the device datasheet.
The ADC can generate both interrupt requests and events. Interrupt requests and events can be
generated either when an ADC conversion is complete or if an ADC measurement is above or
below the ADC Compare register values.
The ADC has a built-in calibration mechanism that calibrates the internal pipeline in the ADC.
The calibration value from the production test must be loaded from the signature row and into
the ADC calibration register from software to obtain best possible accuracy.
• Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility reasons always write these
bits to zero when this register is written
• Bits 2 – CH0START: ADC Start single conversion
Bit
+0x00
Read/Write
Initial Value
R
source
Negative
Positive
input
input
≤
S
is the ADC sample time.
---------------------------------------------- - R
C
sample
R/W
7
–
0
channel
⋅
T
ln
s
(
2
, R
n
R/W
+
6
–
0
1
switch
)
–
and C
channel
R/W
5
–
0
R
R
sample
channel
channel
–
R
switch
refer to the ADC and ADC gain stage electrical charac-
R/W
4
–
0
R/W
3
–
0
R
R
switch
switch
CH0START
R/W
2
0
source
FLUSH
R/W
1
0
, must be less than the
C
C
Sample
Sample
XMEGA D
ENABLE
R/W
0
0
VCC/2
CTRLA
234