ATxmega64D3 Atmel Corporation, ATxmega64D3 Datasheet - Page 265
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ATxmega64D3
Manufacturer Part Number
ATxmega64D3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
18
Input Capture Channels
18
Pwm Channels
18
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA64D3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega64D3-AU
Manufacturer:
JST
Quantity:
1 000
Part Number:
ATxmega64D3-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega64D3-MH
Manufacturer:
Atmel
Quantity:
515
22.4.5.2
22.4.5.3
22.4.5.4
22.4.5.5
22.4.5.6
8210B–AVR–04/10
STS - Store data to PDIBUS Data Space using direct addressing
LD - Load data from PDIBUS Data Space using indirect addressing
ST - Store data to PDIBUS Data Space using indirect addressing
LDCS - Load data from PDI Control and Status Register Space
STCS - Store data to PDI Control and Status Register Space
advantage with the multiple-bytes access is that it gives a way to reduce the protocol overhead.
When using the LDS, the address byte(s) must be transmitted before the data transfer.
The ST instruction is used to store data that is serially shifted into the physical layer shift-register
to locations within the PDIBUS Data Space. The STS instruction is based on direct addressing,
which means that the address must be given as an argument to the instruction. Even though the
protocol is based on byte-wise communication, the ST instruction supports multiple-bytes
address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes,
and long (4 bytes). It should be noted that multiple-bytes access is internally broken down to
repeated single-byte accesses. The main advantage with the multiple-bytes access is that it
gives a way to reduce the protocol overhead. When using the STS, the address byte(s) must be
transmitted before the data transfer.
The LD instruction is used to load data from the PDIBUS Data Space to the physical layer shift-
register for serial read-out. The LD instruction is based on indirect addressing (pointer access),
which means that the address must be stored into the Pointer register prior to the data access.
Indirect addressing can be combined with pointer increment. In addition to read data from the
PDIBUS Data Space, the Pointer register can be read by the LD instruction. Even though the
protocol is based on byte-wise communication, the LD instruction supports multiple-bytes
address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes,
and long (4 bytes). It should be noted that multiple-bytes access is internally broken down to
repeated single-byte accesses. The main advantage with the multiple-bytes access is that it
gives a way to reduce the protocol overhead.
The ST instruction is used to store data that is serially shifted into the physical layer shift-register
to locations within the PDIBUS Data Space. The ST instruction is based on indirect addressing
(pointer access), which means that the address must be stored into the Pointer register prior to
the data access. Indirect addressing can be combined with pointer increment. In addition to write
data to the PDIBUS Data Space, the Pointer register can be written by the ST instruction. Even
though the protocol is based on byte-wise communication, the ST instruction supports multiple-
bytes address - and data access. Four different address/data sizes are supported; byte, word, 3
bytes, and long (4 bytes). It should be noted that multiple-bytes access is internally broken down
to repeated single-byte accesses. The main advantage with the multiple-bytes access is that it
gives a way to reduce the protocol overhead.
The LDCS instruction is used to load data from the PDI Control and Status Registers to the
physical layer shift-register for serial read-out. The LDCS instruction supports only direct
addressing and single-byte access.
The STCS instruction is used to store data that is serially shifted into the physical layer shift-reg-
ister to locations within the PDI Control and Status Registers. The STCS instruction supports
only direct addressing and single-byte access.
XMEGA D
265