SAM3N2C Atmel Corporation, SAM3N2C Datasheet - Page 446
SAM3N2C
Manufacturer Part Number
SAM3N2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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SAM3N
SAM3N
Write Protected Registers
To prevent any single software error that may corrupt SPI behavior, the registers listed below
can be write-protected by setting the SPIWPEN bit in the SPI Write Protection Mode Register
(SPI_WPMR).
If a write access in a write-protected register is detected, then the SPIWPVS flag in the SPI
Write Protection Status Register (SPI_WPSR) is set and the field SPIWPVSRC indicates in
which register the write access has been attempted.
The SPIWPVS flag is automatically reset after reading the SPI Write Protection Status Register
(SPI_WPSR).
List of the write-protected registers:
Section 27.8.2 ”SPI Mode Register”
Section 27.8.9 ”SPI Chip Select Register”
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
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