SAM3N2C Atmel Corporation, SAM3N2C Datasheet - Page 87
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SAM3N2C
Manufacturer Part Number
SAM3N2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.12 Memory access instructions
11011A–ATARM–04-Oct-10
Table 10-17
Table 10-17. Memory access instructions
Mnemonic
ADR
CLREX
LDM{mode}
LDR{type}
LDR{type}
LDR{type}T
LDR
LDREX{type}
POP
PUSH
STM{mode}
STR{type}
STR{type}
STR{type}T
STREX{type}
shows the memory access instructions:
Brief description
Load PC-relative address
Clear Exclusive
Load Multiple registers
Load Register using immediate
offset
Load Register using register offset
Load Register with unprivileged
access
Load Register using PC-relative
address
Load Register Exclusive
Pop registers from stack
Push registers onto stack
Store Multiple registers
Store Register using immediate
offset
Store Register using register offset
Store Register with unprivileged
access
Store Register Exclusive
See
“ADR” on page 88
“CLREX” on page 102
“LDM and STM” on page 97
“LDR and STR, immediate offset” on
page 89
“LDR and STR, register offset” on page
92
“LDR and STR, unprivileged” on page 94
“LDR, PC-relative” on page 95
“LDREX and STREX” on page 100
“PUSH and POP” on page 99
“PUSH and POP” on page 99
“LDM and STM” on page 97
“LDR and STR, immediate offset” on
page 89
“LDR and STR, register offset” on page
92
“LDR and STR, unprivileged” on page 94
“LDREX and STREX” on page 100
SAM3N
87
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