SAM3N2C Atmel Corporation, SAM3N2C Datasheet - Page 656

• Manufacturer Part Number: SAM3N2C
• Manufacturer: Atmel Corporation

Specifications of SAM3N2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 47
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.6.5
33.6.6
656
656
SAM3N
SAM3N
Conversion Triggers
Sleep Mode and Conversion Sequencer
Conversions of the active analog channels are started with a software or hardware trigger. The
software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels or the
external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL
field in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the TRGEN
bit in the Mode Register (ADC_MR).
The minimum time between 2 consecutive trigger events must be strictly greater than the dura-
tion time of the longest conversion sequence according to configuration of registers ADC_MR,
ADC_CHSR, ADC_SEQR1, ADC_SEQR2.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at
each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a
range of 2 MCK clock periods to 1 ADC clock period.
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be pro-
grammed in Waveform Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Reg-
isters permit the analog channels to be enabled or disabled independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are
performed and the resulting data buffers should be interpreted accordingly.
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is
not being used for conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode
Register ADC_MR.
The Sleep mode is automatically managed by a conversion sequencer, which can automatically
process the conversions of all channels at lowest power consumption.
This mode can be used when the minimum period of time between 2 successive trigger events
is greater than the startup period of Analog-Digital converter (See the product ADC Characteris-
tics section).
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the enabled
channels. When all conversions are complete, the ADC is deactivated until the next trigger. Trig-
gers occurring during the sequence are not taken into account.
A fast wake-up mode is available in the ADC Mode Register (ADC_MR) as a compromise
between power saving strategy and responsiveness. Setting the FWUP bit to ‘1’ enables the fast
wake-up mode. In fast wake-up mode the ADC cell is not fully deactivated while no conversion is
requested, thereby providing less power saving but faster wakeup.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
trigger
start
delay
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10