SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 131

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.5.2
Name:
Address:
Access Type:Read-write
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been set to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small. An unreasonably small value breaks every burst and the Bus Matrix spends its time
arbitrating without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMASTR_TYPE: Default Master Type
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in one cycle latency for the first transfer of a burst.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave remains connected to the last mas-
ter that accessed it.
This results in not having the one cycle latency when the last master is trying to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects with the fixed master that
has its index in FIXED_DEFMSTR register.
This results in not having the one cycle latency when the fixed master is trying to access the slave again.
• FIXED_DEFMSTR: Fixed Index of Default Master
This is the index of the Fixed Default Master for this slave.
6062N–ATARM–3-Oct-11
31
23
15
–
–
–
7
Bus Matrix Slave Configuration Registers
MATRIX_SCFG0...MATRIX_SCFG4
0xFFFFEE04
30
22
14
–
–
6
29
21
13
–
–
5
28
20
12
–
–
4
SLOT_CYCLE
FIXED_DEFMSTR
27
19
11
–
–
3
26
18
10
–
–
2
AT91SAM9261
25
17
–
9
–
1
DEFMSTR_TYPE
24
16
–
8
–
0
131