SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 712

• Manufacturer Part Number: SAM9261
• Manufacturer: Atmel Corporation

Specifications of SAM9261

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 160
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.3.9
42.3.9.1
42.3.9.2
42.3.9.3
42.3.10
42.3.10.1
712
AT91SAM9261
SDRAM Controller
Serial Peripheral Interface (SPI)
SDRAM: SDCLK Clock active after reset
SDRAM: JEDEC Standard Compatibility
SDRAM: Mobile SDRAM Device Initialization Constraint
SPI: Pulse Generation on SPCK
After a reset the SDRAM clock is always active leading in over consumption in the pad.
The following sequence allows to stop the SDRAM clock.
In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be stable before the rising
edge of SDCKE. This is not the case in this product.
Use a fully JEDEC compliant SDRAM module.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile
SDRAM device initialization, may lead to data bus contention. Therefore, external memories on
the same EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in sdram to
;perform power down command
;perform proc_reset and periph_reset (in the ARM pipeline)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
complete.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0.
LDR r2, =AT91C_RSTC_RCR
LDR r3, =0xA5000005
STR r1, [r0]
STR r3, [r2]
END
6062N–ATARM–3-Oct-11