SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 193
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SAM9G25
Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G25.pdf
(1147 pages)
5.SAM9G25.pdf
(53 pages)
Specifications of SAM9G25
Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G25 PDF datasheet #4
- SAM9G25 PDF datasheet #5
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- Download datasheet (2Mb)
A.3
ARM DDI0198D
Coprocessor interface signals
Table A-2 describes the ARM926EJ-S processor coprocessor interface signals.
Name
CPABORT
CPBURST[3:0]
CPCLKEN
Coprocessor clock
enable
CPDIN[31:0]
Coprocessor write data
CPDOUT[31:0]
Coprocessor read data
CPEN Coprocessor
enable
CPINSTR[31:0]
Coprocessor
instruction data
CPPASS
CPLATECANCEL
CHSDE[1:0]
Coprocessor
handshake decode
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Output
Output
Output
Input
Output
Input
Output
Output
Output
Output
Description
Indicates
stage of coprocessor pipeline.
attached, this must be tied to b0000.
Coprocessor clock enable. When HIGH on the rising
edge of CLK the pipeline follower logic can
advance.
The coprocessor data bus for transferring data from
the coprocessor.
The coprocessor data bus for transferring data to the
coprocessor.
When LOW disables the external coprocessor
interface. If CPEN is LOW then CHSDE and
CHSEX must both be driven to b10 (ABSENT
response).
The coprocessor instruction bus that instructions are
transferred over to the pipeline follower in the
coprocessor.
Indicates that there is a coprocessor instruction in the
Execute stage of the pipeline, that must be executed.
If HIGH during the first Memory cycle of a
coprocessor instruction, then the coprocessor must
cancel the instruction without changing any internal
state.
The handshake signals from the Decode stage of the
coprocessor pipeline follower. Indicates ABSENT
(b10), WAIT (b00), GO (b01), or LAST (b11). If no
external coprocessors are attached this must be tied to
b10 (ABSENT response).
Indicates number of words to be transferred for
/
Table A-2 Coprocessor interface signals
operation. If no external coprocessors are
/
operation aborted. Asserted in WB
Signal Descriptions
A-5
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