SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 246
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SAM9G25
Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G25.pdf
(1147 pages)
5.SAM9G25.pdf
(53 pages)
Specifications of SAM9G25
Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G25 PDF datasheet #4
- SAM9G25 PDF datasheet #5
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- Download datasheet (2Mb)
Index
Cleaning DCache 9-3
Clock gating 5-32
Coarse page table descriptor 3-11
Context ID register 2-35
Control register 2-12
Conventions
Coprocessor
CPABORT 8-12
CPBURST 8-11
CPU aborts 3-21
CP15
Ctype
D
DCache
Debug
Debug/test address register B-4
Descriptor
Index-2
numerical xx
signal naming xix
timing diagram xviii
typographical xviii
clocking 8-2
instructions 8-3
interface 8-2
interface signals A-5
accessing registers 2-4
MRC and MCR bit pattern 2-4
registers 2-3
test registers B-2
encoding 2-9
field 2-9
enable/disable 2-14
size 2-9
clocks 11-2
override register B-2
signals A-7
support 11-2
coarse page table 3-11
fine page table 3-12
level one 3-8
level two 3-14
section 3-10
Copyright © 2001-2003 ARM Limited. All rights reserved.
Domain 3-3
Drain write buffer 2-21, 9-3
Dsize
DTCM
E
Embedded trace macrocell 10-2
Enable bit (TCM) 2-30
Endianness 6-6
ETM 10-2
Exception vectors 2-14
External aborts 3-29
F
FAR 2-20
Fast context switch 2-34
Fast context switch extension (FCSE)
Fault
Fault address register 2-20, 3-21
Fault status register 2-18, 3-21
FCSE PID register 2-34
FIFOFULL 10-2
Fine page table descriptor 3-12
Format, cache way and set way 4-9
FSR 2-18
H
Halfword accesses 6-6
access control 3-24
access control register 2-17, 3-24
fault 3-27
field 2-19
field 2-9
format 2-9
disabling 5-19
enabling 5-19
interface signals A-12
alignment 3-27
checking sequence 3-26
domain 3-27
permission 3-28
status field encoding 2-20
2-34
I
I and M bit settings
I bit 2-14
ICache
ID cache type register 2-7
ID code register 2-7, 2-8
IMB 9-2
Instruction memory barrier 9-2
Instructions
Interlocked MCR 8-7
Interrupts 8-10
Invalidate
Isize field 2-9
Isize format 2-9
ITCM
J
JTAG signals A-9
L
L bit 2-28
Large page references, translating 3-16
LDC/STC instructions 8-4
Leakage control 12-3
Len field 2-10
DCache 4-6
ICache 4-5
enable/disable 2-14
size 2-9
example sequences 9-5
operation 9-3
MCR 2-4
MRC 2-4
cache 2-21
data TLB 2-25
data TLB single entry 2-25
ICache 9-4
instruction TLB 2-25
single entry 2-21
TLB 2-25
TLB single entry 2-25
disabling 5-19
enabling 5-19
ARM DDI0198D
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