SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 91
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SAM9G25
Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G25.pdf
(1147 pages)
5.SAM9G25.pdf
(53 pages)
Specifications of SAM9G25
Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G25 PDF datasheet #4
- SAM9G25 PDF datasheet #5
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- Download datasheet (2Mb)
3.5.1
3.5.2
3.5.3
ARM DDI0198D
Alignment faults
Translation faults
Domain faults
•
•
•
If alignment fault checking is enabled (the A bit in CP15 c1 is set), the MMU generates
an alignment fault on any data word access if the address is not word-aligned, or on any
halfword access if the address is not halfword-aligned, irrespective of whether the
MMU is enabled or not. An alignment fault is not generated on any instruction fetch or
any byte access.
If an access generates an alignment fault, the access sequence aborts without reference
to other permission checks.
There are two types of translation fault:
Section
Page
There are two types of domain fault:
Section
Page
If the specified access is either no access (00), or reserved (10), then either a section
domain fault or page domain fault occurs.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Translation faults
Domain faults
Permission faults on page 3-28.
Note
A section translation fault is generated if the level one descriptor is
marked as invalid. This happens if bits [1:0] of the descriptor are both 0.
A page translation fault is generated if the level one descriptor is marked
as invalid. This happens if bits [1:0] of the descriptor are both 0.
The level one descriptor holds the four-bit domain field, which selects
one of the 16 two-bit domains in the domain access control register. The
two bits of the specified domain are then checked for access permissions
as described in Table 3-12 on page 3-24. The domain is checked when the
level one descriptor is returned.
The level one descriptor holds the four-bit domain field, which selects
one of the 16 two-bit domains in the domain access control register. The
two bits of the specified domain are then checked for access permissions
as described in Table 3-12 on page 3-24. The domain is checked when the
level one descriptor is returned.
Memory Management Unit
3-27
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