SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 195
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SAM9G25
Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G25.pdf
(1147 pages)
5.SAM9G25.pdf
(53 pages)
Specifications of SAM9G25
Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G25 PDF datasheet #4
- SAM9G25 PDF datasheet #5
- Current page: 195 of 248
- Download datasheet (2Mb)
A.4
ARM DDI0198D
Debug signals
Table A-3 describes the ARM926EJ-S processor debug signals.
Name
COMMRX
Communications
channel receive
COMMTX
Communications
channel transmit
DBGACK
Debug acknowledge
DBGDEWPT
Data watchpoint
DBGEN
Debug enable
DBGEXT[1:0]
EmbeddedICE-RT
external input
DBGIEBKPT
Instruction breakpoint
DBGINSTREXEC
Instruction executed
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Output
Output
Output
Input
Input
Input
Input
Output
Description
When HIGH, this signal denotes that the comms
channel receive buffer contains valid data waiting to
be read.
When HIGH, this signal denotes that the comms
channel transmit buffer is empty.
When HIGH indicates that the processor is in debug
state.
Asserted by external hardware to halt execution of
the processor for debug purposes. If HIGH at the end
of a data memory request cycle, it causes the
ARM926EJ-S processor to enter debug state.
Enables the debug features of the processor. This
signal must be tied LOW if debug is not required.
Inputs to the EmbeddedICE-RT logic that enable
breakpoints or watchpoints to be dependent on
external conditions.
Asserted by external hardware to halt execution of
the processor for debug purposes. If HIGH at the end
of an instruction fetch, it causes the ARM926EJ-S
processor to enter debug state if that instruction
reaches the Execute stage of the processor pipeline.
Indicates that the instruction in the Execute stage of
the processor pipeline has been executed.
Table A-3 Debug signals
Signal Descriptions
A-7
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